Below you can find a list of publications related to Scheduled Dataflow, listed in
reverse chronological order. If you want a copy of any of these publications, please
contact Dr. Krishna Kavi by email at kavi@cse.unt.edu.
- L. Song, Y. Zhang and K.M. Kavi. "A simple loop transformation for multithreaded,
superscalar and VLIW architectures", Proceedings of the 16th International Conference
on Parallel and Distributed Computing Systems (PDCS-2003, sponsored by the International
Society for Computers and their Applications, ISCA), Aug. 3-15,2003, Reno, Nevada,
USA.
- Litong Song and K.M. Kavi. "A technique for variable dependent driven loop peeling",
Proceedings of the 5th International Conference on Algorithms and Architectures for
Parallel Processing (IC3APP2K2), Beijing, China, Oct. 23-25, 2002.
- Joseph Arul and K.M. Kavi. "Scalability of Scheduled Dataflow Architecture ( SDF)
with register contexts", Proceedings of the 5th International Conference on Algorithms
and Architectures for Parallel Processing (IC3APP2K2), Beijing, Chin a, Oct. 23-25,
2002.
- K.M. Kavi, J. Arul and R. Giorgi. "Performance Evaluation of a Non-Blocking Multithreaded
Architecture for Embedded, Real-Time and DSP Applications", Proceedings of the ISCA
PDCS-2001, Dallas Texas, August 8-11, 2001, pp 365-371.
- K.M. Kavi, R. Giorgi and J. Arul. "Scheduled Dataflow: Execution paradigm, architecture
and performance evaluation", IEEE Transactions on Computers, Vol. 50, No. 8, August
2001, pp 834-846.
- K.M. Kavi, J. Arul and R. Giorgi. "Execution and cache performance of the Scheduled
Dataflow Architecture", Journal of Universal Computer Science, Special Issue on Multithreaded
and Chip Multiprocessors, Oct. 2000.
- J. Arul, K.M. Kavi and S. Hanief. "Cache Performance of Scheduled Dataflow Architecture",
Proc. of the 4th International Conference on Algorithms and Architectures for Parallel
Processing (ICA3PP2000), Hong Kong, Dec. 11-14, 2000.
- K.M. Kavi, R. Giogi and J. Arul. "Comparing execution performance of Scheduled Dataflow
Architecture with RISC processors", Proc. of the 13th ISCA Parallel and Distributed
Computing Systems Conference (PDCS-00), Published by the International Society of
Computers and Their Applications, Las Vegas, Aug. 8-10, 2000, pp 41-47.
- J. Arul, K.M. Kavi and S. Hanief. "Cache Performance of Scheduled Dataflow Architecture",
Proc. of the 4th International Conference on Algorithms and Architectures for Parallel
Processing (ICA3PP2000), Hong Kong, Dec. 11-14, 2000, pp 110-123.
- K.M. Kavi, J. Arul and R. Giorgi. "Execution and cache performance of the Scheduled
Dataflow Architecture", Journal of Universal Computer Science, Special Issue on Multithreaded
and Chip Multiprocessors, Oct. 2000, pp 948-967.
- K.M. Kavi, R. Giogi and J. Arul. "Comparing execution performance of Scheduled Dataflow
Architecture with RISC processors", Proc. of the 13th ISCA Parallel and Distributed
Computing Systems Conference (PDCS-00), Published by the International Society of
Computers and Their Applications, Las Vegas, Aug. 8-10, 2000.
- H.Y. Kim, K.M. Kavi and A.R. Hurson. "A Simple Non-Blocking Architecture", Proc. ISCA
12th International Conference on Parallel and Distributed Computing Systems (PDCS-99),
Ft. Lauderdale, FL, Aug. 18-20, 1999 pp 231-236.
- K.M. Kavi. H.S. Kim and A.R. Hurson. "Scheduled dataflow architecture: A synchronous
execution paradigm for dataflow", IASTED Journal of Computers and Applications. Vol.
21, No. 3 (Oct. 1999), pp 114-124.
- K.M. Kavi, H.-S.Kim, J. Arul and A.R. Hurson "A decoupled scheduled dataflow multithreaded
architecture", Proceedings of the 1999 International Symposium on Parallel Architectures,
Algorithms and Networks (I-SPAN99), Fremantle, Western Australia, June 23-25, 1999,
pp 138-143.
- K.M. Kavi, D. Levine and A.R. Hurson. "PL/PS: A non-blocking multithreaded architecture",
Proceedings of the the Fifth International Conference on Advanced Computing (ADCOMP-97),
Madras, India, Dec. 1997, pp 171-177.
- K.M. Kavi. "Multithreaded System Implementations", IASTED Journal of Microcomputer
Applications, Vo. 18, No. 2, 1999.
- K.M. Kavi, B. Lee and Ali Hurson. "Multithreaded systems: A survey", Advances in Computers
(Edited by M. Zerkowitz), Vo. 46, 1998.
- A.R. Hurson, J.T. Lim, K.M. Kavi and B. Lee "Parallelization of DOALL and DOACROSS
loops - a survey", Advances in Computers, Vol. 45 (Edited by M. Zerkowitz), Academic
Press 1997, pp 54-105.
- A.R. Hurson, K.M. Kavi, B. Shirazi and B. Lee. "Cache Memories in Dataflow Architectures:
A Survey", IEEE Parallel and Distributed Technology, Winter 1996, pp 50-64.
- K.M. Kavi and A.R. Hurson. "Performance of cache memories in dataflow architectures",
Euromicoro Journal on Systems Architecture, Vol. 44, No. 1, March 1998.
- A.R. Hurson, K.M. Kavi and J.T. Lim. "Cyclic Staggering Scheme: A loop allocation
policy for DOACROSS loops", IEEE Transactions on Computers, Feb. 1998.
- K.M. Kavi and A.R. Hurson. "Investigation of operand memory reuse in a dynamic dataflow
architecture", Proceedings of the High Performance Computing Symposium 96, April 8-11,
1996, New Orleans, Louisiana.
- K.M. Kavi and A.R. Hurson. "Cache Memories in Dataflow Architecture", Proceedings
of the 7th IEEE Symposium on Parallel and Distributed Processing, Oct. 25-27, 1995,
San Antonio, TX, pp 182-189..
- K.M. Kavi, A.R. Hurson, P. Patadia, E. Abraham and P. Shanmugam. "Design of cache
memories for multi-threaded dataflow architecture", Proceedings of the 22nd Intl.
Symposium. on Computer Architecture (ISCA-22), June 1995, St. Margherita Ligure, Italy.
- P. Shanmugam, S. Andhare, K.M. Kavi, B. Shirazi and A.R. Hurson. "Cache memory for
an explicit token store dataflow architecture", Proceedings of the 5th IEEE symposium
on parallel and distributed processing pp 45-50 (Dec1-3, 1993, Dallas, Texas)
- V. Karani, P. Patadia, K.M. Kavi, P. Shanmugam, B. Shirazi and A.R. Hurson. "Improvements
to the ETS dynamic dataflow architecture", Proceedings of the 27th Hawaii International
Conference on Systems Sciences, HICSS-27 Vol. 1, pp 378-387 (Maui, HI, Jan 4-7, 1994).
- K. M. Kavi and B. Shirazi. "Dataflow Architecture: Are dataflow computers commercially
viable?", IEEE Potentials, Oct. 1992, pp 27-30
- B. Lee and K.M. Kavi. "Program partitioning for multithreaded dataflow computers",
Proc. of 26th Hawaii International Conference on System Sciences (HICSS-26), Jan.
5-8, 1993, pp II 487-495.
- B. Shirazi. and K.M. Kavi. "A new cache coherency and address translation consistency
protocol", Proc. of 1992 Intl Conference on Parallel Processing.